1. Field of the Invention
The present invention is generally related to general purpose, stored program, digital computers and more particularly relates to efficient means for performing Built-In-Self-Tests (BIST) on internal memory elements.
2. Description of the Prior Art
A key design element of high reliability computer systems is Built-In-Self-Test (BIST). The complexity of computer systems has increased exponentially over the past several decades. Because of this increased complexity, many of the internal nodes within modern computer systems are not controllable or observable from the external I/O pins. BIST design techniques have been developed to combat this growing problem. BIST can be used to make the internal nodes of a complex computer system both controllable and observable and therefore testable. This is the only method of ensuring hardware integrity in many modern computer systems.
One method for providing BIST is to replace the functional registers within a design with serial scan shift registers. The serial scan shift registers can operate in both a functional mode and a test mode. During normal operations, the serial scan shift registers are placed in functional mode and operate like any other flip-flop. In test mode, the serial scan shift registers are configured into a scan path which allows test data to be "serially shifted" through the registers within the design.
Typically, Automatic Test Equipment (ATE) scans in computer generated serial scan test vectors through the serial scan shift registers within the design. Once these vectors are fully shifted into the design, the data residing in the serial scan shift registers then travels through the logic gates and eventually arrives at either an I/O pin or another serial scan shift register. The serial scan shift registers are then switched into functional mode and the clock is pulsed once. The functional clock causes the serial scan shift registers to capture the data that has traveled through the logic gates. The serial scan shift registers are then switched back into test mode and the results are shifted out and compared to an expected value. This process is repeated until an adequate fault coverage is obtained.
A technique that is used for automating the latter part of this process is to provide a signature analysis register within the design. The signature analysis register is coupled to predetermined nodes within the design. As a predefined pattern is shifted through the design, the signature analysis register is updated periodically. At the end of the test, the contents of the signature analysis register are compared to an expected "signature". If there is a match, the system is deemed to be fully functional. This eliminates the need to compare the results of the serial scan vectors with an expected result and therefore may eliminate the need for expensive Automatic test Equipment (ATE).
The serial scan techniques described above are commonly used for testing logic gates within a design. However, this techniques is not efficient for testing large memory elements like Random Access Memories (RAMs). RAMs typically have a large number of address locations which require several different patterns to be written to each address location to ensure that there are no "stuck" bits, addresses, and/or data lines. To serially shift-in and shift-out test vectors for each address location/pattern combination would require a relatively large amount of time.
Computer systems today require large amounts of Random Access Memory to operate efficiently. Both the Application program and the resulting data are often stored in RAM. Therefore, it is common to have a large array of RAM devices located on a memory card or equivalent within a computer system. The RAM devices located therein have become increasingly large. Today each RAM device can store one megabyte (1 MB) of data or more. Consequently, the number of memory addresses which must be tested in today's computer systems can be very large. One can readily see that it would be advantageous to test the numerous RAM devices within a computer system in parallel rather than serially.
One method for performing functional tests on a memory device is described in U.S. Pat. No. 5,138,619 issued to Fasang et al. This method utilizes a first pseudo random number generator (PRNG) to generate the address inputs and a second PRNG to generate the data inputs. A parallel signature analyzer is used to generate a signature based upon the results of the test. If the resulting signature matches a known correct signature then the memory is deemed to be fully functional. The drawbacks of this approach are that it requires a substantial amount of support circuitry and it can only test one RAM device at a time.
A similar method for performing functional tests on a memory device is described in U.S. Pat. No. 4,903,266 issued to Hack. Hack suggests a method that allows the PRNG to generate all capable memory address including the all zeros address. It is unclear whether Fasang can achieve the all zeros address. Like Fasang, Hack also utilizes a signature analysis register to determine RAM functionality. As a result, Hack has the same drawbacks as Fasang.
Another method for testing memory elements is described in U.S. Pat. No. 4,835,774 issued to Ooshima et al. Ooshima provides test data from a modified pattern generator to identical address in both the memory under test and a redundant buffer memory device. The contents of the memory under test and the buffer memory device are then read out and compared. If the data is not identical, the memory under test is rejected as defective. This method is most likely used in a semiconductor production facility for testing many identical RAM devices with Automatic Test Equipment. It is clear that this method requires a substantial amount of test hardware including a redundant buffer memory device. In addition, this method only contemplates testing one RAM device at a time.
A related method for testing memory devices is described in U.S. Pat. No. 4,788,684 issued to Kawaguchi et al. Kawaguchi suggests a method for testing a memory device having a first and a second memory block. Kawaguchi provides for an auxiliary pattern generator which stores the data that is provided to the memory device. The contents of the memory device are then read out and compared to the contents stored in the auxiliary pattern generator. If the data is not identical, the memory device is rejected as defective. Kawaguchi, like Ooshima, requires a substantial amount of test hardware including an auxiliary pattern generator for storing input data. In addition, Kawaguchi only contemplates testing one RAM device at a time.
Another method for testing memory devices is described in U.S. Pat. No. 4,788,684 issued to Benton et al. However, unlike Ooshima and Kawaguchi, Benton suggests a means for regenerating the data pattern that was written to a particular address thus eliminating the need for additional test memory to store input data. Benton also suggests a means for comparing the regenerated data with the actual data read from the memory device. Although Benton does not require additional test memory, Benton does require a complex circuit for regenerating the data contained at a given address. In addition, Benton does not contemplate testing more than one memory device at a time.